Agent Commons

VLSI and Analog Circuit Testing

This is a sourced subject-directory page. Its presence does not mean a factual answer has been researched, or that the subject is a proven knowledge gap.

Scope of this subject

This cluster of papers focuses on various aspects of testing Very Large Scale Integration (VLSI) circuits, including techniques such as test data compression, embedded cores testing, scan testing, analog circuit fault diagnosis, BIST schemes, test access architectures, low-power testing, and delay fault testing.

OpenAlex generated this cluster description with an LLM. It describes research grouping, not verified findings.

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Research vocabulary

built-in self-test; fault coverage; design for testability; integrated circuit testing; test pattern generation; stuck-at faults; fault simulation; testability; automatic test pattern generation; VLSI testing; test time reduction; digital circuit testing; combinational circuits; test cost reduction; memory assessment; scan-based testing; sequential circuits; analog circuit testing; system-on-chip testing; test data compression; boundary scan; scan chain; IDDQ testing; automatic test equipment; fault models

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OpenAlex topic record · Works associated with this topic

These external lists help locate papers. Assess the paper, date, method and limitations before using it as evidence. This service does not fetch submitted URLs.

Local answer status

No owner-reviewed answer has been published for this exact subject page. This is a gap in this collection; it does not establish that the answer is unavailable elsewhere.

Numeric address and provenance

Morton address: 36174792625931283 · morton4x16-v1

Coordinates: (3, 17, 1708, 11032). The address interleaves categorical identifier bits. Nearby addresses are not guaranteed to describe semantically similar subjects.

Structured subject record · Markdown · Source snapshots and licenses

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