{"cited_by_count":440510,"description":"This cluster of papers focuses on various aspects of testing Very Large Scale Integration (VLSI) circuits, including techniques such as test data compression, embedded cores testing, scan testing, analog circuit fault diagnosis, BIST schemes, test access architectures, low-power testing, and delay fault testing.","display_name":"VLSI and Analog Circuit Testing","domain_id":"3","external_ids":{"openalex":"https://openalex.org/T11032","wikipedia":"https://en.wikipedia.org/wiki/Very_Large_Scale_Integration#Testing"},"field_id":"17","id":"T11032","keywords":[{"display_name":"built-in self-test","id":"built-in-self-test","score":0.8175,"url":"https://openalex.org/keywords/built-in-self-test"},{"display_name":"fault coverage","id":"fault-coverage","score":0.7824,"url":"https://openalex.org/keywords/fault-coverage"},{"display_name":"design for testability","id":"design-for-testability","score":0.6653,"url":"https://openalex.org/keywords/design-for-testability"},{"display_name":"integrated circuit testing","id":"integrated-circuit-testing","score":0.6635,"url":"https://openalex.org/keywords/integrated-circuit-testing"},{"display_name":"test pattern generation","id":"test-pattern-generation","score":0.8299,"url":"https://openalex.org/keywords/test-pattern-generation"},{"display_name":"stuck-at faults","id":"stuck-at-faults","score":0.7361,"url":"https://openalex.org/keywords/stuck-at-faults"},{"display_name":"fault simulation","id":"fault-simulation","score":0.4306,"url":"https://openalex.org/keywords/fault-simulation"},{"display_name":"testability","id":"testability","score":0.3689,"url":"https://openalex.org/keywords/testability"},{"display_name":"automatic test pattern generation","id":"automatic-test-pattern-generation","score":0.8289,"url":"https://openalex.org/keywords/automatic-test-pattern-generation"},{"display_name":"VLSI testing","id":"vlsi-testing","score":0.8454,"url":"https://openalex.org/keywords/vlsi-testing"},{"display_name":"test time reduction","id":"test-time-reduction","score":0.4183,"url":"https://openalex.org/keywords/test-time-reduction"},{"display_name":"digital circuit testing","id":"digital-circuit-testing","score":0.7733,"url":"https://openalex.org/keywords/digital-circuit-testing"},{"display_name":"combinational circuits","id":"combinational-circuits","score":0.364,"url":"https://openalex.org/keywords/combinational-circuits"},{"display_name":"test cost reduction","id":"test-cost-reduction","score":0.4092,"url":"https://openalex.org/keywords/test-cost-reduction"},{"display_name":"memory assessment","id":"memory-testing","score":0.2737,"url":"https://openalex.org/keywords/memory-testing"},{"display_name":"scan-based testing","id":"scan-testing","score":0.878,"url":"https://openalex.org/keywords/scan-testing"},{"display_name":"sequential circuits","id":"sequential-circuits","score":0.23,"url":"https://openalex.org/keywords/sequential-circuits"},{"display_name":"analog circuit testing","id":"analog-circuit-testing","score":0.8936,"url":"https://openalex.org/keywords/analog-circuit-testing"},{"display_name":"system-on-chip testing","id":"system-on-chip-testing","score":0.9308,"url":"https://openalex.org/keywords/system-on-chip-testing"},{"display_name":"test data compression","id":"test-data-compression","score":0.888,"url":"https://openalex.org/keywords/test-data-compression"},{"display_name":"boundary scan","id":"boundary-scan","score":0.8261,"url":"https://openalex.org/keywords/boundary-scan"},{"display_name":"scan chain","id":"scan-chain","score":0.776,"url":"https://openalex.org/keywords/scan-chain"},{"display_name":"IDDQ testing","id":"iddq-testing","score":0.9154,"url":"https://openalex.org/keywords/iddq-testing"},{"display_name":"automatic test equipment","id":"automatic-test-equipment","score":0.2738,"url":"https://openalex.org/keywords/automatic-test-equipment"},{"display_name":"fault models","id":"fault-models","score":0.277,"url":"https://openalex.org/keywords/fault-models"}],"legacy_keywords":["Test Data Compression","Embedded Cores","Scan Testing","Analog Circuit Fault Diagnosis","BIST Scheme","Test Access Architecture","Low-Power Testing","Test Vector Compression","System-on-a-Chip Test","Delay Fault Testing"],"openalex_id":"https://openalex.org/T11032","source_created_date":"2024-01-23T15:27:09","source_updated_date":"2026-10-17T03:02:00","subfield_id":"1708","url":"/topics/T11032","works_api_url":"https://api.openalex.org/works?filter=topics.id:T11032","works_count":56512,"label":"VLSI and Analog Circuit Testing","provider":"openalex","revision":"423467d50a782972","taxonomy_revision":"f050b5d4780b1289","title":"VLSI and Analog Circuit Testing","kind":"topic-directory","aeo_cohort":"topic-directory","catalogue_revision":"f050b5d4780b1289","numeric_address":"36174792625931283","address_version":"morton4x16-v1","coordinates":[3,17,1708,11032],"answer_status":"Directory metadata; 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