Electrostatic Discharge in Electronics
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Scope of this subject
This cluster of papers focuses on the design, analysis, and modeling of electrostatic discharge (ESD) protection in integrated circuits, particularly in CMOS technology. It covers topics such as SCR devices, LDMOS design, RF ESD protection, TLP calibration, high-voltage ESD solutions, and latchup immunity. The papers also discuss on-chip protection strategies and system-level ESD testing.
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Research vocabulary
electrostatic discharge; electrostatic discharge protection; latch-up; ESD robustness; holding voltage; on-chip ESD protection; ESD protection devices; ESD testing; transmission line pulse; ESD protection circuits; IEC 61000-4-2; charged device model; electrical overstress; trigger voltage; latch-up immunity; electrostatic discharge robustness; ESD damage; electrostatic discharge immunity; electrostatic discharge testing; machine model; transmission line pulse testing; ESD immunity; electrostatic protection; failure current; ESD protection circuit design
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Local answer status
No owner-reviewed answer has been published for this exact subject page. This is a gap in this collection; it does not establish that the answer is unavailable elsewhere.
Numeric address and provenance
Morton address: 38350968936630969 · morton4x16-v1
Coordinates: (3, 22, 2208, 12495). The address interleaves categorical identifier bits. Nearby addresses are not guaranteed to describe semantically similar subjects.
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